1. Field of the Invention
This invention relates to ferroelectric field effect transistors, and more particularly to ferroelectric memories utilizing such transistors and methods of operating such transistors and memories.
2. Statement of the Problem
It has been known since at least the 1950""s that if a practical ferroelectric memory could be made, it would provide a fast, dense, non-volatile memory that could be operated at relatively low voltages. See Orlando Auciello, et al., xe2x80x9cThe Physics of Ferroelectric Memoriesxe2x80x9d, Physics Today, July 1998, pp. 22-27. The principal type of ferroelectric memory being explored today is the non-volatile ferroelectric random access memory or NVFRAM. Ibid. A disadvantage of the NVFRAM is that, in the process of reading it, the information it holds is destroyed and, therefore, the read function must be followed by a rewrite function. However, it has been postulated for at least 40 years that it may be possible to design a memory in which the memory element is a ferroelectric field effect transistor (FET), which memory could be non-destructively read. See Shu-Yau Wu, xe2x80x9cA New Ferroelectric Memory Device, Metal-Ferroelectric-Semiconductor Transistorxe2x80x9d, in IEEE Transactions On Electron Devices, pp. 499-504, August 1974; S. Y. Wu, xe2x80x9cMemory Retention and Switching Behavior Of Metal-Ferroelectric-Semiconductor Transistorsxe2x80x9d, in Ferroelectrics, Vol. 11, pp. 379-383, 1976; and J. R. Scott, C.A. Paz De Araujo, and L. D. McMillan, xe2x80x9cIntegrated Ferroelectricsxe2x80x9d, in Condensed Matter News, Vol. 1, No. 3, pp. 15-20, 1992. Because the ferroelectric memory effect measured in the early devices of Wu was only a temporary, single state effect rather than a long lived two state effect, it is now believed that this effect was charge injection effect rather than an effect due to ferroelectric switching. However, recently a metal-ferroelectric-insulator-semiconductor FET device, i.e. a MFISFET, has been reported that appears to show true ferroelectric memory behavior. See Tadahiko Hirai, et al., xe2x80x9cFormation of Metal/Ferroelectric/Insulator/Semiconductor Structure With A CeO2 Buffer Layerxe2x80x9d, in Japan Joumal of Applied Physics, Vol. 33, Part I, No. 9B, pp. 5219-5222, September 1994; Tadahiko Hirai, et al., xe2x80x9cCharacterization of Metal/Ferroelectric/Insulator/Semiconductor Structure With A CeO2 Buffer Layerxe2x80x9d, in Japan Journal of Applied Physics, Vol. 34, Part I, No. 8A, pp. 4163-4166, August 1995; Yong Tae Kim, et al., xe2x80x9cMemory Window of Pt/SrBi2Ta2O9/CeO2/SiO2/Si Structure For Metal Ferroelectric Insulator Semiconductor Field Effect Transistorxe2x80x9d, Applied Physics Letters, Vol. 71 No. 24, Dec. 15, 1997, pp. 3507-3509; and U.S. Pat. No. 5,744,374 issued Apr. 28, 1998 to Jong Moon.
To make a memory requires not only a memory element, but also a means for addressing a large number of memory elements. Initially, it was believed that a ferroelectric memory element might be addressed by a simple array of rows and columns of conductors. A ferroelectric memory element, it was thought, could be located at each of the junctures of the array and addressed by applying a voltage to the conductors for the corresponding row and column. It was believed that if the voltage on each conductor was less than the threshold voltage for ferroelectric switching (coercive voltage) and the voltage difference between the conductors was greater than the coercive voltage, then only the selected cell would be written to or read, and the other cells would remain unchanged. However, it was found that this did not work because the neighboring unselected cells were disturbed by the voltages on the address lines. Thus, a switch was added between one of the address lines and each ferroelectric memory element. See U.S. Pat. No. 2,876,436 issued on Mar. 3, 1959 to J. R. Anderson and U.S. Pat. No. 4,873,664 issued on Oct. 10, 1989 to S. Sheffield Eaton, Jr. If the switch is a transistor as in the latter patent, the memory assumes a memory address architecture essentially the same as that of a conventional DRAM. However, when applied to a ferroelectric memory, even this architecture disturbed the memory cells attached to the same plate line as the addressed cell. That is, it has been found that ferroelectric materials do not have a sharp coercive threshold voltage, but rather even a small voltage will cause the ferroelectric to partially switch and, therefore, the repetitive application of small disturb voltages, such as occur in a conventional memory array, eventually causes the change or loss of a memory state. Therefore, a more complex architecture was proposed to overcome this disturb. See, for example, U.S. Pat. No. 4,888,733 issued on Dec. 19, 1989 to Kenneth J. Mobley.
The above address schemes are all for a NVFRAM; that is, a memory utilizing a ferroelectric capacitor as a memory element, rather than for a memory utilizing a ferroelectric FET. Insofar as known to applicants, the only address architecture disclosed up to now for a memory in which the memory element is a ferroelectric FET is shown in FIG. 1 of U.S. Pat. No. 5,523,964 issued on Jun. 4, 1996 to McMillan, et al. Like the Mobley, et al., architecture, to avoid the disturb problem, this architecture is relatively complex, utilizing five transistors in each memory cell in addition to the ferroelectric FET. Such complex architecture results in a memory that is much less dense and slower than, for example, a conventional DRAM. Thus, it appears that the fact that the ferroelectric material does not have a sharp coercive field threshold and can be switched by repetitive applications of a small voltage has made several of the original objectives of research into ferroelectric memories unattainable. It would, therefore, be highly desirable to provide a simpler architecture and method for addressing a ferroelectric memory.
The invention solves the above problem by providing a method and apparatus for addressing a ferroelectric memory in which there are no additional electric elements in the individual memory cell; that is, it provides an architecture in which each memory cell preferably contains only the ferroelectric memory element, e.g. the ferroelectric FET.
A memory cell can be written to by applying an electrical pulse to the gate and an electrical bias between another two electrical elements of the cell.
In the preferred embodiment, the ferroelectric memory element is a ferroelectric FET and a write bias is applied between the substrate and a FET source/drain.
In one preferred embodiment, a source/drain of all cells in an array are held at a common voltage and the substrate voltage is used to select the cells to be written to. Preferably, the drain voltage is used to select which logic state is to be written to an individual cell.
A truth table provides a unique drain to source current for each combination of write bias with the pulse on the gate. A unique logic state is associated with the unique drain to source current.
Preferably, the cell is read by sensing the source/drain current when a voltage difference is placed across the source and drain.
New ferroelectric memory cell structures and fabrication processes are also provided to ensure that the substrate of each cell can be electrically isolated from the substrate of the other cells.
The invention provides a method of writing to a selected memory cell in a ferroelectric memory, the memory including a plurality of memory cells each containing a ferroelectric FET, each of the ferroelectric FETs having a first electrical element and a second electrical element, the ferroelectric FETs arranged in an array comprising a plurality of rows and a plurality of columns of the ferroelectric FETs, the memory further including a plurality of first row lines, each of the first row lines running parallel to one of the rows of the ferroelectric FETs, and a plurality of column lines, each of the column lines running parallel to one of the columns of ferroelectric FETs, the method comprising placing a first voltage on the one of the row lines running parallel to the one of the rows containing the selected memory cell, placing a second voltage on the one of the columns running parallel to the selected memory cell, applying the first voltage to the first electrical element in each of the ferroelectric FETs in the row containing the selected memory cell, and applying the second voltage to the second electrical element in each of the ferroelectric FETs in the column containing the selected memory cell. Preferably, the first electrical element is the source of the FETs. Preferably, the first electrical element is the substrate of the FETs. Preferably, the first electrical element is the drain of the FETs. Preferably, the second electrical element is the source of the FETs. Preferably, the second electrical element is the substrate of the FETs. Preferably, the second electrical element is the gate of the FETs. Preferably, the second electrical element is the drain of the FETs. Preferably, the second electrical element is the gate of the FETs. Preferably, the first electrical element is the gate of the FETs. Preferably, the second electrical element is the substrate of the FETs. Preferably, each of the ferroelectric FETs include a third electrical element and the memory further includes a plurality of second row lines, each of the second row lines running parallel to one of the rows of the ferroelectric FETs, and the method further comprises placing a third voltage on the one of the second row lines running parallel to the row containing the selected memory cell and applying the third voltage to the third electrical element in each of the ferroelectric FETs in the row containing the selected memory cell. Preferably, the third electrical element is the drain of the FETs. Preferably, each of the ferroelectric FETs include a third electrical element and the memory further includes a plurality of second row lines, each of the second row lines running parallel to one of the rows of the ferroelectric FETs, and the method further comprises placing a third voltage on the one of the second row lines running parallel to the row containing the selected memory cell and applying the third voltage to the third electrical element in each of the ferroelectric FETs in the row containing the selected memory cell.
The invention also provides a method of reading a ferroelectric memory including a plurality of ferroelectric FETs, the method comprising the steps of: sensing a first current through an electrical element of a first one of the FETs; sensing a second current through an electrical element of a second one of the FETs, the first current being greater than the second current; and associating a first logic state with the first current and a second logic state with the second current. Preferably, the method further comprises the steps of sensing a third current through an electrical element of a third one of the FETs, the third current being of opposite sign to the first current; and associating the second logic state with the third current. Preferably, the electrical element is either the source or the drain of the FET.
In addition, the invention provides a method of reading a ferroelectric memory including a plurality of ferroelectric FETs, the method comprising the steps of: sensing a first current through an electrical element of a first one of the FETs; sensing a second current through an electrical element of a second one of the FETs, the second current being of opposite sign to the first current; and associating a first logic state with the first current and a second logic state with the second current.
The invention further provides a ferroelectric memory, the memory including a plurality of memory cells each containing a ferroelectric FET, each of the ferroelectric FETs having a first electrical element and a second electrical element, the ferroelectric FETs arranged in an array comprising a plurality of rows and a plurality of columns of the ferroelectric FETs, the memory further including a plurality of first row lines, each of the first row lines running parallel to one of the rows of the ferroelectric FETs, and a plurality of column lines, each of the column lines running parallel to one of the columns of ferroelectric FETs, each of the first row lines electrically connected to the first electrical element in one of the rows of ferroelectric FETs, and each of the column lines electrically connected to the second electrical element in one of the columns of ferroelectric FETs. Preferably, the first electrical element is the source of the FETs. Preferably, the first electrical element is the substrate of the FETs. Preferably, the first electrical element is the drain of the FETs. Preferably, the second electrical element is the source of the FETs. Preferably, the second electrical element is the substrate of the FETs. Preferably, the second electrical element is the gate of the FETs. Preferably, the second electrical element is the drain of the FETs. Preferably, the second electrical element is the gate of the FETs. Preferably, the first electrical element is the gate of the FETs. Preferably, the second electrical element is the substrate of the FETs. Preferably, each of the ferroelectric FETs include a third electrical element and the memory further includes a plurality of second row lines, each of the second row lines running parallel to one of the rows of the ferroelectric FETs, each of the second row lines electrically connected to the third electrical element in one of the rows of ferroelectric FETs. Preferably, the third electrical element is the drain of the FETs. Preferably, each of the ferroelectric FETs include a third electrical element and the memory further includes a plurality of second row lines, each of the second row lines running parallel to one of the rows of the ferroelectric FETs, each of the second row lines electrically connected to the third electrical element in one of the rows of ferroelectric FETs.
In a further aspect, the invention provides a ferroelectric memory comprising a plurality of ferroelectric FETs arranged in a plurality of rows and a plurality of columns; a row decoder electrically connected to a first electrical element of each of the ferroelectric FETs; and a column decoder electrically connected to a second electrical element of each of the ferroelectric FETs. Preferably, the first electrical element is the gate of each FET and the second electrical element is the substrate of each FET. Preferably, the first electrical element is the substrate of each FET and the second electrical element is the gate of each FET. Preferably, the first electrical element is the gate of each FET and the second electrical element is the drain of each FET. Preferably, the first electrical element is the drain of each FET and the second electrical element is the substrate of each FET. Preferably, the first electrical element is the substrate of each FET and the second electrical element is the drain of each FET. Preferably, the ferroelectric FET comprises a FET selected from the group consisting of: a MFISFET, a MFMISFET, and a MFSFET.
In still a further aspect, the invention provides a ferroelectric memory comprising a memory array comprising a plurality of rows and columns of memory cells wherein each of the memory cells consisting essentially of a single electrical component, the single electrical component consisting essentially of a ferroelectric FET. Preferably, the ferroelectric FET comprises a FET selected from the group consisting of: a MFISFET, a MFMISFET, and a MFSFET. Preferably, the memory further includes a row decoder for addressing the rows and a column decoder for addressing the columns.
In still another aspect, the invention provides a ferroelectric memory comprising a first ferroelectric FET having a first semiconducting substrate and second ferroelectric FET having a second semiconducting substrate, the memory further including a substrate insulator insulating the first semiconducting substrate from the second semiconducting substrate. Preferably, the memory comprises an array of rows and columns of the ferroelectric FETs, each of the FETs having a semiconducting substrate, and the insulator insulates each of the semiconducting substrates from all of the other semiconducting substrates. Preferably, the memory further includes an electrical contact to each of the semiconducting substrates. Preferably, the memory includes a plurality of wells in the insulator and the contact comprises a conductive layer in each of the wells.
In yet another aspect, the invention provides a ferroelectric memory cell comprising: a semiconducting substrate, a first well formed in the substrate; a second well formed in the first well; and a ferroelectric FET, a portion of which is formed in the second well; the first well and the second well comprising different semiconductor types. Preferably, the first semiconductor type is n-type semiconductor and the second semiconductor type is p-type semiconductor. Preferably, the portion of the FET formed is the second well comprises a source/drain.
In still a further aspect, the invention provides a method of writing to a selected memory cell in a ferroelectric memory comprising a plurality of memory cells, each of the memory cells comprising a ferroelectric FET comprising a substrate, a gate, a source/drain, and a channel, the substrate and the source/drain forming a junction diode having a threshold voltage, the method comprising the step of forward biasing the junction diode whereby the voltage at the channel essentially comprises the threshold voltage of the junction diode. Preferably, the threshold voltage ranges from 0.2 volts to 0.7 volts.
In a further aspect, the invention provides a method of writing to a selected memory cell in a ferroelectric memory comprising a plurality of memory cells, each of the memory cells comprising a ferroelectric FET comprising a substrate, a gate, a source/drain, and a channel, the substrate and the source/drain forming a junction diode having a threshold voltage, the method comprising the step of reverse biasing the junction diode whereby the voltage at the channel is essentially unaffected by a voltage applied to the source/drain.